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general description the ds3902 features a dual, nonvolatile (nv), low tem- perature-coefficient, variable digital resistor with 256 user-selectable positions. the ds3902 can operate over a wide supply range of 2.4v to 5.5v, and commu- nication with the device is achieved through an i 2 c- compatible serial interface. internal address settings allow the ds3902 slave address to be programmed to one of 128 possible addresses. the low cost and the small size of the ds3902 make it an ideal replacement for conventional mechanical-trimming resistors. applications optical transceivers optical transponders instrumentation and industrial controls rf power amps audio power-amp biasing replacement for mechanical variable resistors and dip switches features ? dual 256-position linear digital resistors ? available as 50k ? /30k ? or 50k ? /15k ? ? resistor settings stored in nv memory ? low temperature coefficient ? i 2 c-compatible serial interface ? wide operating voltage (2.4v to 5.5v) ? software write protection ? user-eeprom memory ? programmable slave address ? operating temperature range: -40? to +95? ? small 8-pin ?op package ds3902 dual, nv, variable resistors with user eeprom ______________________________________________ maxim integrated products 1 scl sda add_sel 1 gnd 2-wire master 4.7k ? 4.7k ? 0.1 f h1 h0 v cc v cc v cc v cc out- out+ bias+ bias- md in+ in- tx_fault tx_disable biasmax 2 apcset 2 modset 2 pc_mon bs_mon bias set mod set notes: 1. with add_sel tied to gnd, the slave address will be a2h. 2. for a detailed application diagram of a specific ld, consult the laser driver data sheet. laser driver ic ds3902 t ypical operating circuit rev 0; 5/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * add /t&r for tape & reel orders. ordering information pin configuration appears at end of data sheet. part resistor values (r0, r1) top brand pin- package ds3902u-530 30k ? , 50k ? 3902a 8 ?op DS3902U-515 15k ? , 50k ? 3902b 8 ?op i 2 c is a trademark of philips corp. purchase of i 2 c components of maxim integrated products, inc., or one of its associated companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the sys- tem conforms to the i 2 c standard specification as defined by philips.
ds3902 dual, nv, variable resistors with user eeprom 2 _____________________________________________________________________ absolute maximum ratings recommended dc operating conditions (t a = -40? to +95?) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc , sda, scl, h0, and h1 relative to ground................................-0.5v to +6.0v voltage range on add_sel relative to ground ...............-0.5v to (v cc + 0.5v), not to exceed 6.0v resistor current ....................................................................3ma operating temperature range ...........................-40? to +95? programming temperature range .........................0? to +70? storage temperature range .............................-55? to +125? soldering temperature ...............................................see ipc/jedec j-std-020a specification parameter symbol conditions min typ max units supply voltage v cc (note 1) +2.4 +5.5 v input logic 1 ( sda, scl, add_sel) v ih 0.7 x v cc v cc + 0.3 v input logic 0 ( sda, scl, add_sel) v il -0.3 +0.3 x v cc v resistor inputs h0, h1 -0.3 +5.5 v resistor current i res 3ma dc electrical characteristics (v cc = +2.4v to +5.5v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units standby current i stby (note 2) 200 ? input leakage i l -1 +1 ? v ol1 3ma sink current 0 0.4 low-level output voltage (sda) v ol2 6ma sink current 0 0.6 v analog resistor characteristics (v cc = +2.4v to +5.5v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units resistance tolerance t a = +25? -20 +20 % position 0 resistance 160 250 ? absolute linearity (note 3) -1 +1 lsb relative linearity (note 4) -0.75 +0.75 lsb temperature coefficient at position ffh. (notes 5, 6) -300 +300 ppm/? high-impedance resistor current i rhiz h0, h1 = v cc -1 +1 ?
ds3902 dual, nv, variable resistors with user eeprom _____________________________________________________________________ 3 ac electrical characteristics (figure 1) (v cc = +2.4v to +5.5v, t a = -40? to +95?, unless otherwise noted. timing referenced to v il(max) and v ih(min) .) note 1: all voltages referenced to ground. note 2: i stby specified for the inactive state measured with sda = scl = v cc , add_sel = gnd, and with h0 and h1 floating. note 3: absolute linearity is the difference of measured value from expected value at resistor position. expected value is from the measured minimum position to measured maximum position. note 4: relative linearity is the deviation of an lsb resistor setting change vs. the expected lsb change. expected lsb slope of the straight line is the typical operating curves from the measured minimum position to measured maximum position. note 5: see the typical operating characteristics section. note 6: guaranteed by design. note 7: timing shown is for fast-mode (400khz) operation. this device is also backward-compatible with i 2 c standard mode. note 8: c b ?otal capacitance of one bus line in picofarads. note 9: eeprom write begins after a stop condition occurs. parameter symbol conditions min typ max units scl clock frequency f scl (note 7) 0 400 khz bus free time between stop and start conditions t buf 1.3 ? hold time (repeated) start condition t hd:sta 0.6 ? low period of scl t low 1.3 ? high period of scl t high 0.6 ? data hold time t hd:dat 0 0.9 ? data setup time t su:dat 100 ? start setup time t su:sta 0.6 ? sda and scl rise time t r (note 8) 20 + 0.1 x c b 300 ns sda and scl fall time t f (note 8) 20 + 0.1 x c b 300 ns stop setup time t su:sto 0.6 ? sda and scl capacitive loading c b (note 8) 400 pf eeprom write time t wr (note 9) 10 ms input capacitance c i 5pf startup time t st (note 6) 2 ms nonvolatile memory characteristics (v cc = +2.4v to +5.5v, unless otherwise noted.) parameter symbol conditions min typ max units eeprom writes +70? (note 6) 50,000
ds3902 dual, nv, variable resistors with user eeprom 4 _____________________________________________________________________ t ypical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.) standby supply current vs. temperature ds3902 toc01 temperature ( c) standby supply current ( a) 80 60 20 40 0 -20 20 40 60 80 100 120 140 160 180 0 -40 v cc = +5v v cc = +3v asel = gnd h0, h1, open sda = scl = v cc supply current vs. scl frequency ds3902 toc02 scl frequency (khz) supply current ( a) 350 300 200 250 100 150 50 20 40 60 80 100 120 140 160 180 200 0 0400 v cc = sda = +5v resistance vs. resistor setting ds3902 toc03 resistor setting (dec) resistance ( ? ) 250 225 175 200 50 75 100 125 150 25 5 10 15 20 25 30 35 40 45 50 0 0 h1 h0 (-530 version) temperature coefficient vs. position ds3902 toc04 position (dec) temperature coefficient (ppm/ c) 250 200 150 100 50 0 200 400 600 800 1000 1200 1400 1600 -200 0 tc of +25 c to -40 c tc of +25 c to +85 c position ffh resistance percent change from +25 c vs. temperature ds3902 toc05 temperature ( c) resistance % change (from +25 c) 80 60 40 20 0 -20 0 0.2 0.4 0.6 0.8 -0.2 -40 position 00h resistance percent change from +25 c vs. temperature ds3902 toc06 temperature ( c) resistance % change (from +25 c) 80 60 20 40 0 -20 -8 -6 -4 -2 0 2 4 6 8 10 12 -10 -40 h0, h1 resistance vs. power-up voltage ds3902 toc07 power-up voltage (v) resistance ( ? ) 5 4 3 2 1 10 20 30 40 50 60 70 80 90 100 0 0 h0 (-530 version) eeprom recall >100k h1 programmed resistance (ffh) h0, h1 resistance vs. power-down voltage ds3902 toc08 power-down voltage (v) resistance ( ? ) 5 4 3 2 1 10 20 30 40 50 60 70 80 90 100 0 0 h0 (-530 version) >100k h1 programmed resistance (ffh) position 7fh resistance vs. supply voltage ds3902 toc09 supply voltage (v) position 7fh resistance ( ? ) 5.4 4.9 3.9 4.4 3.4 2.9 12 14 16 18 20 22 24 26 28 30 10 2.4 h1 h0 (-530 version)
ds3902 dual, nv, variable resistors with user eeprom _____________________________________________________________________ 5 t ypical operating characteristics (continued) (v cc = +3.3v, t a = +25?, unless otherwise noted.) h0 absolute linearity vs. position ds3902 toc10 position (dec) h0 absolute linearity (lsb) 250 200 150 100 50 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0 0 h0 relative linearity vs. position ds3902 toc11 position (dec) h0 relative linearity (lsb) 250 200 150 100 50 0.02 0.04 0.06 0.08 0.1 0 0 h1 absolute linearity vs. position ds3902 toc12 position (dec) h1 absolute linearity (lsb) 250 200 150 100 50 0.02 0.04 0.06 0.08 0.1 0 0 h1 relative linearity vs. position ds3902 toc13 position (dec) h1 relative linearity (lsb) 250 200 150 100 50 0.02 0.04 0.06 0.08 0.1 0 0
ds3902 dual, nv, variable resistors with user eeprom 6 _____________________________________________________________________ detailed description the block diagram of the ds3902 is shown in the block diagram section. detailed descriptions of major com- ponents follow. memory map a memory map of the ds3902 is shown in table 1. resistors the ds3902 contains two, 256-position (plus high-z), nv, variable digital resistors. pins h0 and h1 are the high terminals of resistor 0 and resistor 1, respective- ly. the low terminals of both resistors are tied to ground internally. the resistors are programmed using the i 2 c serial interface (see the resistor 0 and resistor 1 regis- pin description pin name function 1h0re sistor 0 high terminal 2 sda i 2 c serial-data open-drain input/output 3 scl i 2 c serial-clock input 4 gnd ground 5 add_sel address select 6h1re sistor 1 high terminal 7n .c. no connection 8v cc power-supply voltage block diagram ds3902 sda slave address 00h resistor 0 02h resistor 1 msbyte lsbyte 03h 04-05h password entry (ram) 06-07h password setting 10-1fh user memory (16 bytes) device memory (eeprom) msb lsb 01h r1 r0 hi-z resistor 0 256 position 30k or 15k ? h0 high-z 8 8 8 7 xxxxxx scl gnd v cc v cc i 2 c interface add_sel resistor 1 256 position 50k ? h1 hi-z
ds3902 dual, nv, variable resistors with user eeprom _____________________________________________________________________ 7 ters in the memory map). the configuration register contains a bit (r0 and r1) for each resistor to enable the high-z state. when one of the high-z bits is written to a ?? the corresponding resistor goes high-z. when written back to a ?? the resistor goes back to the pro- grammed resistance. writing the resistor 0 or resistor 1 register to 00h, sets the respective resistor to its mini- mum position (and minimum resistance). this value can be found in the analog resistor characteristics electri- cal table . writing resistor 0 or resistor 1 to ffh, sets the resistor to its maximum resistance. the nominal resistance (in ohms) of the resistors can be found in the ordering information table at the beginning of this data sheet. when the ds3902 is powered up, the resistors are both set to high-z instantaneously while the settings stored in eeprom are recalled. slave address & add_sel pin the i 2 c slave address of the ds3902 depends on the state of the add_sel pin. if this pin is low, then the slave address is a2h. if the add_sel pin is high, then the slave address is determined by the value stored in eeprom at address 00h. refer to the memory map to see the factory default of the slave address. the seven most significant bits are used (the lsb is not used because it is in the bit position of the r/ w bit) to allow the slave address to be programmed to one of 128 possible addresses. the i 2 c interface is described in detail in a later section. software write protection software write protection is enabled by creating a two byte password and writing it to the password setting register (06h to 07h). when write protected, all memory locations can be read, but only the password entry reg- ister (04h to 05h) can be written. when the correct password is entered, then the memory can be written to. refer to the memory map to see which registers can be read/written with and without the password (pw). when shipped from the factory, the password setting is ffffh. likewise, every time the device is powered-up the password entry register (which is ram, not eep- rom) defaults to ffffh, giving full access to the device. if write protection is not desired, then leave the password setting at the factory default and ignore the password entry register. i 2 c serial interface description i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses, start, and stop conditions. slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic high states. when the bus is idle it often initi- ates a low-power mode for slave devices. table 1. memory map binary access description addr msb lsb factory default w/o pw w/pw type slave address 00h slave address x a0h r r/w eeprom configuration 01h xxxxxxr1r0 00h r r/w eeprom resistor 0 02h b7 b6 b5 b4 b b2 b1 b0 7fh r r/w eeprom resistor 1 03h b7 b6 b5 b4 b3 b2 b1 b0 7fh r r/w eeprom 04h pw msb ffh password entry 05h pw lsb ffh ww ram 06h pw msb ffh password setting 07h pw lsb ffh r/w eeprom no memory 08h 0fh user memory 10h 1fh 16 bytes of general purpose eeprom all ffh r r/w eeprom x = don? care.
ds3902 dual, nv, variable resistors with user eeprom 8 _____________________________________________________________________ sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start note: timing is referenced to v il (max) and v ih (min) figure 1. i 2 c timing diagram start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see the timing dia- gram for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see the timing dia- gram for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it immediately initiates a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identi- cally to a normal start condition. see the timing dia- gram for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements (see figure 1). data is shifted into the device during the rising edge of the scl. bit read: at the end a write operation, the master must release the sda bus line for the proper amount of setup time (see figure 1) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowledge- ment (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. a device performs a nack by transmitting a one during the 9th bit. timing (figure 1) for the ack and nack is identical to all other bit writes. an ack is the acknowledg- ment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8-bits of informa- tion transferred from the master to the slave (msb first) plus a 1-bit acknowledgement from the slave to the master. the 8-bits transmitted by the master are done according to the bit write definition and the acknowl- edgement is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (msb first) from the slave to the master are read by the master using the bit read defini- tion above, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate com- munication so the slave will return control of sda to the master.
ds3902 dual, nv, variable resistors with user eeprom _____________________________________________________________________ 9 slave address byte: each slave on the i 2 c bus responds to a slave addressing byte sent immediately following a start condition. the slave address byte contains the slave address in the most significant 7-bits and the r/ w bit in the least significant bit. the ds3902? slave address depends on the state of the add_sel pin. if add_sel is low, then the slave address byte is a2h, where the lsb is the r/ w bit. if the r/ w bit is 0 (such as in a2h), then master indicates it will write data to the slave. if r/ w = 1 (a3h in this case), the master will read data from the slave. if an incorrect slave address is written, the ds3902 will assume the master is communicating with another i 2 c device and ignore the communication until the next start condition is sent. on the other hand, if the add_sel pin is a logic high, then the slave address byte is determined by the slave address register saved in eeprom (address 00h). the lsb of the register is not used since it is in the bit loca- tion of the r/ w bit. refer to the slave address and add_sel pin section for more information. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte trans- mitted during a write operation following the slave address byte. i 2 c communication writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data and generate a stop condition. remember the master must read the slave? acknowl- edgement during all byte write operations. writing multiple bytes to a slave: to write multiple bytes to a slave the master generates a start condi- tion, writes the slave address byte (r/ w = 0), writes the memory address, writes up to 2 data bytes and gener- ates a stop condition. the ds3902 is capable of writing 1 or 2 bytes (1 page or row) with a single write transaction. this is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. the address counter limits the write to one 2-byte page. attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row. each row begins on even memory addresses. to prevent address wrapping from occurring, the mas- ter must send a stop condition at the end of the page, and then wait for the bus free or eeprom write time to elapse. then the master may generate a new start condition, write the slave address byte (r/ w = 0), and the first memory address of the next memory row before continuing to write data. acknowledge polling: any time an eeprom page is written, the ds3902 requires the eeprom write time (t w ) after the stop condition to write the contents of the page to eeprom. during the eeprom write time, the device will not acknowledge its slave address because it is busy. it is possible to take advantage of that phe- nomenon by repeated addressing the ds3902, which allows the next page to be written as soon as the ds3902 is ready to receive the data. the alternative to acknowledge polling is to wait for maximum period of t w to elapse before attempting to write again to the device. eeprom write cycles: when eeprom writes occur, the ds3902 will write the whole eeprom memory page even if only a single byte on the page was modified. writes that do not modify all 2-bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. because the whole page is written, bytes on the page that were not modified dur- ing the transaction are still subject to a write cycle. this can result in a whole page being worn out over time by writing a single byte repeatedly. writing a page one byte at a time will wear the eeprom out two times faster than writing the entire page at once. the ds3902? eeprom write cycles are specified in the nonvolatile memory characteristics table. the specifi- cation shown is at the worst case temperature. it is capable of handling approximately 10x that many writes at room temperature. reading a single byte from a slave: unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. manipulating the address counter for reads: a dummy write cycle can be used to force the address counter to a particular value. to do this the master gen- erates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condi- tion, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition.
ds3902 dual, nv, variable resistors with user eeprom 10 ____________________________________________________________________ see figure 2 for a read example using the repeated start condition to specify the starting memory location. reading multiple bytes from a slave: the read oper- ation can be used to read multiple bytes with a single transfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another byte before terminating the transaction. after the master reads the last byte it nacks to indicate the end of the transfer and generates a stop condition. this can be done with or without modifying the address counter? location before the read cycle. application information using the resistors as a switch by taking advantage of the resistor? high-impedance state, the resistors can be used as a digitally controlled switch. setting the resistor to position 0 is equivalent to a logic low level. by using an external pull-up resistor, a logic high level can be generated by setting the resistor to the high-z state. power supply decoupling to achieve best results, it is highly recommended that a decoupling capacitor is used on the ic power supply pins. typical values of decoupling capacitors are 0.01? and 0.1?. use a high-quality, ceramic, surface-mount capacitor, and mount it as close as possible to the v cc and gnd pins of the ic to minimize lead inductance. slave address* start start 1 0 1 0 0 0 1 r/w slave ack slave ack slave ack msb lsb msb lsb msb lsb b7 b6 b5 b4 b3 b2 b1 b0 read/ write register address b7 b6 b5 b4 b3 b2 b1 b0 data stop single byte write -write resistor 0 to mid position (7fh) single byte write -set resistor 1 to hi-z single byte read -read resistor 1 two byte write - enter the password. start stop 1 0100010 00000 100 a2h 04h start repeated start a3h master nack stop 1 0100010 00000 011 03h 10100 011 1 0100010 00000 010 a2h 02h stop res value start 1 0100010 00000 001 a2h 01h stop data 02h 7fh example 2-wire transactions (when add_sel tied to gnd) typical 2-wire write transaction * the address is determined by the add_sel pin. the examples assume add_sel is tied to gnd. if the add_sel pin were instead connected to v cc . then the address would be determined by the slave address register. 01111 111 0 0 000 010 a2h pw msb pw lsb two byte read - read both resistors in one transaction. a) c) b) d) d) start stop 101000 10 000 00010 a2h 02h a3h 1010 0011 res 0 data res 1 d ata slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack master ack master nack repeated start figure 2. i 2 c communication examples
ds3902 dual, nv, variable resistors with user eeprom maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 11 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. dallas is a registered trademark of dallas semiconductor corporation. pac ka ge information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . h1 add_sel gnd 1 2 8 7 v cc n.c. sda scl h0 sop top view 3 4 6 5 ds3902 pin configuration chip topology transistor count: 11252 substrate connected to ground

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